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| PIC17CXX EPROM Memory Programming Specification This document includes the programming specifications for the following devices: * PIC17C42 * PIC17C42A * PIC17CR42 * PIC17C43 * PIC17CR43 * PIC17C44 Pin Diagram 40L PDIP, Windowed CERDIP VDD RC0/AD0 RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 VSS RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB6 RB7 OSC1/CLKIN OSC2/CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RD0/AD8 RD1/AD9 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 MCLR/VPP VSS RE0/ALE RE1/OE RE2/WR TEST RA0/INT RA1/T0CKI RA2 RA3 RA4/RX/DT RA5/TX/CK 1.0 PROGRAMMING THE PIC17CXX The PIC17CXX is programmed using the TABLWT instruction. The table pointer points to the internal EPROM location start. Therefore, a user can program an EPROM location while executing code (even from internal EPROM). This programming specification applies to PIC17CXX devices in all packages. For the convenience of a programmer developer, a "program & verify" routine is provided in the on-chip test program memory space, the program resides in ROM and not EPROM. Therefore, it is not erasable. The "program/verify" routine allows the user to load any address, program a location, verify a location or increment to the next location. It allows variable programming pulse width. PIC17CXX 1.1 Hardware Requirements The PIC17CXX requires two programmable power supplies, one for VDD (2.5V to 6.0V recommended) and one for VPP (13 0.25V). Both supplies should have a minimum resolution of 0.25V. The PIC17CXX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". Three times (3X) additional pulses will increase program margin then beyond VDD (max.) and insure safe operation in user system. Since the PIC17CXX under programming is actually executing code from "boot ROM," a clock must be provided to the part. Furthermore, the PIC17CXX under programming may have any oscillator configuration (EC, XT, LF or RC). Therefore, the external clock driver must be able to overdrive pulldown in RC mode. CMOS drivers are required since the OSC1 input has a Schmitt trigger input with levels (typically) of 0.2VDD and 0.8VDD. See the PIC17C4X data sheet (DS30412A) for exact specifications. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC17C42/42A/43/44 During Programming Pin Name RA <0:4> TEST RB <7:0> RC <7:0> MCLR/VPP VDD VSS Pin Name RA <0:4> TEST PAD <15:8> PAD <7:0> VPP VDD VSS Pin Type I I I/O I/O P P P Pin Description Necessary in programming mode Must be set to "high" to enter programming mode Address & data: high byte Address & data: low byte Programming Power Power Supply Ground Legend: I = Input, O = Output, P = Power 1996 Microchip Technology Inc. DS30139I-page 1 This document was created with FrameMaker 4 0 4 PIC17CXX The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP=VDD range required during programming. VDD min.=minimum operating VDD spec for the part. VDD max.=maximum operating VCC spec for the part. Programmers must verify the PIC17CXX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC17CXX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. Note: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. All unused pins during programming are in high impedance state. PORTB (RB) has internal weak pull-ups which are active during the programming mode. When TEST pin is high, Power-up timer (PWRT) and Oscillator Start-up Timers (OST) are disabled. 2.1 Program/Verify Mode The program/verify mode is intended for full-feature programmers. This mode offers the following capabilities: a) b) c) d) Load any arbitrary 16-bit address to start program and/or verify at that location. Increment address to program/verify the next location. Allows arbitrary length programming pulse width. Following a "verify" allows option to program the same location or increment and verify the next location. Following a "program" allows options to program the same location again, verify the same location or to increment and verify the next location. 2.0 PROGRAM MODE ENTRY To execute the programming routine, the user must hold TEST pin high, RA2, RA3 must be low and RA4 must be high (after power-up) while keeping MCLR low and then raise MCLR pin from VIL to VDD or VPP. This will force FFE0h in the program counter and execution will begin at that location (the beginning of the boot code) following reset. Execution is forced to Internal mode by overriding the fuse configuration. The code protect bit is not overwritten. The program immediately polls PORT RB<7:0> to determine a branch address. Presenting E1h on PORT RB will cause the program to jump to and execute the "program/verify" routine. e) FIGURE 2-1: PROGRAMMING/VERIFY STATE DIAGRAM Pulse RA1 Increment Address Reset Jump to Program Routine Pulse RA1 Load Address Verify Pulse RA1 Pulse RA1 (Raise RA1 after RA0) RA0 Raise RA1 before RA0 Program Pulse RA0 (RA0 pulse width is programming time) DS30139I-page 2 (c) 1996 Microchip Technology Inc. EPROM Memory Programming Specification 2.1.1 LOADING NEW ADDRESS 2.1.3 PROGRAM CYCLE The program allows new address to be loaded right out of reset. A 16-bit address is presented on ports RB (high byte) and RC (low byte) and the RA1 is pulsed (0 1, then 1 0). The address is latched on the rising edge of RA1. See timing diagrams for details. After loading an address, the program automatically goes into a "verify cycle". To load a new address at any time, the PIC17C4X must be reset and the programming mode re-entered. 2.1.2 VERIFY (OR READ) MODE "Program cycle" is entered from "verify cycle" or program cycle" itself. After a verify, pulsing RA0 will begin a program cycle. 16-bit data must be presented on PORTS RB (high byte) and RC (low byte) before RA0 is raised. The data is sampled 3 TCY cycles after the rising edge of RA0. Programming continues for the duration of RA0 pulse. At the end of programming the user can choose one of three different routes. If RA1 is kept low and RA0 is pulsed again, the same location will be programmed again. This is useful for applying over programming pulses. If RA1 is raised before RA0 falling edge, then a verify cycle is started without address increment. Raising RA1 after RA0 goes low will increment address and begin verify cycle on the next address. "Verify mode" can be entered from "Load address" mode, "program mode" or "verify mode". In verify mode pulsing RA1 will turn on PORTS RB and RC output drivers and output the 16-bit value from the current location. Pulsing RA1 again will increment location count and be ready for the next verify cycle. Pulsing RA0 will begin a program cycle. FIGURE 2-2: PIC17C4X PROGRAM MEMORY MAP 0000 On chip Program EPROM FOSC0 FOSC1 WDTPS0 WDTPS1 PM0 Reserved PM1 Reserved FE00 FE01 FE02 FE03 FE04 FE05 FE06 FE07 FE08 FE09 FE0F 07FF FE00 FE0F Configuration Word Reserved Reserved PM2* FFFF *This location does not exist for PIC17C42 (c) 1996 Microchip Technology Inc. DS30139I-page 3 PIC17CXX 3.0 PROGRAMMING SPECIFICATIONS PROGRAMMING ROUTINE FLOWCHART Reset No FIGURE 3-1: RA2 = 0 RA3 = 0 RA4 = 1 RA1 =0 Yes MCLR = 1 B port = 0xE1 (hold for 10 Tcy) No RA1 =1 Yes Present address on ports RB, RC hold Tcy after RA1 changes to 1 No RA1 =0 Yes No RA1 =0 Yes Read MSB of data from port-B. Read LSB of data from port-C. Enable RA0 to end prog cycle B & C ports not driven by part No RA1 =1 Yes Program 16 bit data If programming is desired, force port B = MSB of data force port C = LSB of data (hold 10Tcyc after RA0 is raised) No RA0 = 0 Yes RA1 =0 Yes Yes RA0= 1 Yes RA0= 1 No RA1 =1 No Yes Stop driving address on port No No Increment Address Yes No RA1 =0 Yes No RA1 =1 No RA1 =1 Yes B port = xxx - B port is forced by the part B port = MSB of Data C port = LSB of Data B port = xxx - B port is tri-state, should be forced by user Min RA1 high or low = 10 Tcy DS30139I-page 4 (c) 1996 Microchip Technology Inc. EPROM Memory Programming Specification FIGURE 3-2: RECOMMENDED PROGRAMMING ALGORITHM FOR USER EPROM Start Load new address Pulse-count = 0 Set VDD = VDD min Verify blank Pass Blank check? No Issue "Blank check fail" error message Yes Load new data Programming error: Issue error message "Fail verify @ VDDmin/max" "Fail verify @ VDD min/max" Set VDD = VDDmin Set VDD = VDDP Yes Program using 100s pulse increment pulse-count Pass? No Set VDD = VDD max. VDDmax Set Verify location(s) Verify location for correct data Set VDD = VDD min Set VDD = VDDmin Verify location Yes Pass? Apply (3 x Pulse-count) more 100 s programming pulses for margin (Over programming) No No Pulsecount >25 Location fails programming, issue error message "Unable to program location" (c) 1996 Microchip Technology Inc. DS30139I-page 5 PIC17CXX FIGURE 3-3: RECOMMENDED PROGRAMMING ALGORITHM FOR CONFIGURATION WORDS Start Load new address Pulse-count = 0 Set VDD = VDDmin Verify blank Pass Blank check? Yes No Issue "blank check fail" error message Load new data Set VDD = VDDmin Programming error: Issue error message "Fail verify @ VDDmin/max" Set VDD = VDDP Yes Program using 100 s pulse increment pulse-count Pass? No Yes Pulse count <100 No Set VDD = VDDmax Verify location(s) Verify location for correct data Set VDD = VDDmin Set VDD = VDDmin Verify location Yes Pass? No Location fails programming, issue error message "Unable to program location" DS30139I-page 6 (c) 1996 Microchip Technology Inc. EPROM Memory Programming Specification 4.0 CONFIGURATION WORD Configuration bits are mapped into program memory. Each bit is assigned one memory location. In erased condition a bit will read as '1'. To program a bit, the user needs to write to the memory address. The data is immaterial; the very act of writing will program the bit. The configuration word locations are shown in Table 4-3. The programmer should not program the reserved locations to avoid unpredictable results and to be compatible with future variations of the PIC17C4X. It is also mandatory that configuration locations are programmed in the strict order starting from the first location (0xFE00) and ending with the last (0xFE0F). Unpredictable results may occur if the sequence is violated. (PORTC). PAD<15:8> (PORTB) will be set to 0xFF. Reading a configuration location between 0xFE08 and 0xFE0F will place the high byte of the configuration word into PAD<7:0> (PORTC). PAD<15:8> (PORTB) will be set to 0xFF. TABLE 4-1: Bit FOSC0 FOSC1 CONFIGURATION BIT PROGRAMMING LOCATIONS Address 0xFE00 0xFE01 0xFE02 0xFE03 0xFE04 0xFE06 0xFE0F WDTPS0 WDTPS1 PM0 PM1 PM2 This 4.1 Reading Configuration Word The PIC17CXX has seven configuration locations (see Table 4-1). These locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. Reading any configuration location between 0xFE00 and 0xFE07 will place the low byte of the configuration word (see Table 4-2) into PAD<7:0> location does not exist on the PIC17C42. TABLE 4-2: 15 1 15 1 14 1 14 1 READ MAPPING OF CONFIGURATION BITS 13 1 13 1 12 1 12 1 11 1 11 1 10 1 10 1 9 1 9 1 8 1 8 1 7 -- 7 PM2* 6 PM1 6 -- 5 -- 5 -- 4 3 2 1 0 PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 4 -- 3 -- 2 -- 1 -- 0 -- --=Unused PM<2:0>, Processor Mode Select bits 111 = Microprocessor mode 110 = Microcontroller mode 101 = Extended Microcontroller mode 000 = Code protected microcontroller mode WDTPS<1:0>, WDT Prescaler Select bits. 11 = WDT enabled, postscaler = 0 10 = WDT enabled, postscaler = 256 01 = WDT enabled, postscaler = 64 00 = WDT disabled, 16-bit overflow timer FOSC<1:0>, Oscillator Select bits 11 = EC oscillator 10 = XT oscillator 01 = RC oscillator 00 = LF oscillator * This bit does not exist on PIC17C42. (c) 1996 Microchip Technology Inc. DS30139I-page 7 PIC17CXX 4.2 Embedding Configuration Word Information in the Hex File To allow portability of code, a PIC17C4X programmer is required to read the configuration word locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the hex file, it should be to address FE00h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-3: CONFIGURATION WORD PIC17C42 To code protect: * Protect all memory XXXXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory PIC17C42A To code protect: * Protect all memory 0XXXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory PIC17CR42 To code protect: * Protect all memory 0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory PIC17C43 To code protect: * Protect all memory 0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory PIC17CR43 To code protect: * Protect all memory 0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory PIC17C44 To code protect: * Protect all memory 0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Program Memory Segment Configuration Word (0xFE00) All memory Legend: X = Don't care *Write to on-chip EPROM memory is disabled. The only way these locations can be programmed is if a TABLWT instruction is issued from an "on-chip" program memory space to program an on-chip memory location. DS30139I-page 8 (c) 1996 Microchip Technology Inc. EPROM Memory Programming Specification 4.3 CHECKSUM COMPUTATION The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. TABLE 4-4: CHECKSUM COMPUTATION Code Protect MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode Blank Value 0xF7FF 0xF7EF 0xF7BF 0xF7AF 0xF95F 0xF94F 0xF91F 0xF80F 0xF95F 0xF94F 0xF91F 0xF80F 0xF15F 0xF14F 0xF11F 0xF00F 0xF15F 0xF14F 0xF11F 0xF00F 0xE15F 0xE14F 0xE11F 0xE00F 0xC0DE at 0 and max address 0x79BD 0x79AD 0x797D 0xBB73 0x7B1D 0x7B0D 0x7ADD 0xBBD3 0x7B1D 0x7B0D 0x7ADD 0xBBD3 0x731D 0x730D 0x72DD 0xB3D3 0x731D 0x730D 0x72DD 0xB3D3 0x631D 0x630D 0x62DD 0xA3D3 Device PIC17C42 Checksum* SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM_XNOR8[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM_XNOR8[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM_XNOR8[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM_XNOR8[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM_XNOR8[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM_XNOR8[0x000:0x1FFF] + CFGW & 0x015F PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_XNOR8(a:b) = [Sum of 8-bit wide XNOR copied into upper and lower byte, of locations a to b inclusive] *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND (c) 1996 Microchip Technology Inc. DS30139I-page 9 PIC17CXX 5.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE +10C TA +70C, unless otherwise stated, (25C is recommended) 4.5V VDD 5.25V, unless otherwise stated. Characteristic Supply voltage during programming Supply current during programming Supply voltage during verify Min. 4.75 Typ. 5.0 Max. 5.25 50 VDD min. 12.75 VDD max. 13.25 Units V mA V Freq = 10MHz, VDD = 5.5V Note 3 Note 2 Conditions/Comments Standard Operating Conditions Operating Temperature: Operating Voltage: Parameter No. PD1 PD2 PD3 PD4 PD6 P1 P2 P3 P4 P5 Sym. VDDP IDDP VDDV VPP P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 Note 1: Note 2: Note 3: Voltage on VPP/MCLR pin V Note 1 during programming IPP Programming current on 25 50 mA Note 3 VPP/MCLR pin FOSCP Osc/clockin frequency dur4 10 MHz ing programming TCY Instruction cycle 1 0.4 s TCY = 4/FOSCP TirV2tsH RA0, RA1, RA2, RA3, RA4 1 s setup before TEST TtsH2mcH TEST to MCLR 1 s TbcV2irH RC<7:0>, RB<7:0> valid to 0 s RA1 or RA0 :Address/Data input setup time s 10 TCY TirH2bcl RA1 or RA0 to RB<7:0>, RC<7:0> invalid ; Address data hold time; T0ckiL2rbc RT to RB<7:0>, RC<7:0> 8 TCY Z high impedance T0ckiH2bcV RA1 to data out valid 10 TCY Tprog Programming pulse width 10 100 1000 s TirH2irL RA0, RA1 high pulse width 10 TCY s TirL2irH RA0, RA1 low pulse width 10 TCY s T0ckiV2inL RA1 before INT (to go 0 s from prog cycle to verify w/o increment) 10 TCY s TinL2rtl RA1 valid after RA0 (to select increment or no increment going from program to verify cycle s Note 1 Tvpps VPP setup time before RA0 100 Tvpph VPP hold time after INT 0 s Note 1 TvdV2tsH VDD stable to TEST 10 ms TrbV2mcH RB input (E1h) valid to VPP/ 0 s MCLR TmcH2rbI RB input (E1h) hold after ns 10 TCY VPP/MCLR TvpL2vdL VDD power down after VPP 10 ms power down VPP/MCLR pin must only be equal to or greater than VDD at times other than programming. Program must be verified at the minimum and maximum VDD limits for the part. These parameters are for design guidance only and are not tested nor characterized. DS30139I-page 10 (c) 1996 Microchip Technology Inc. FIGURE 5-1: Test 13V tvpps P14 P15 P9 (c) 1996 Microchip Technology Inc. tvppH tirH2lrL P11 P10 tprog tirL2lrH INC ADDR P8 P7 VPP/MCLR 5V P4 ttsH2mcH P3 tirV2tsH RA1 tra1H2bcV tra1L2bcZ P18 RA0 tmcH2rbL P17 trbV2mcH ADDR_HI DATA_HI OUT DATA_HI OUT DATA_HI_IN DATA_HI OUT PROGRAMMING AND VERIFY TIMINGS I RB<7:0> E1H Jump Address Input ADDR_LO DATA_LO OUT DATA_LO OUT RC<7:0> DATA_LO_IN P5 DATA_LO OUT tbcV2irH P6 tirH2bcI Programming Mode entry Load address X Verify location X Increment address to X + 1 by pulsing RA1 Verify location X + 1 Program location X + 1 Do not increment PC by raising RA1 before RA0 Verify location X + 1 EPROM Memory Programming Specification Note: RA2 = 0 RA3 = 0 RA4 = 1 DS30139I-page 11 FIGURE 5-2: DS30139I-page 12 P14 P15 PIC17CXX Test 13V 5V tvpps P9 P9 P9 VPP/MCLR tvppH tprog tprog tprog RA1 RA0 PROGRAMMING AND VERIFY TIMINGS II RB<7:0> ADDR_HI DATA_HI OUT DATA_HI_IN DATA_HI_IN E1H Jump Address Input ADDR_LO DATA_LO_IN DATA_LO OUT DATA_LO_IN DATA_HI_IN DATA_HI OUT RC<7:0> DATA_LO_IN DATA_LO OUT Programming mode entry Load address X Verify location X Program location X Program location X Move to verify cycle Prevent increment of PC by raising RA1 before RA0 Verify location X (c) 1996 Microchip Technology Inc. Note: RA2 = 0 RA3 = 0 RA4 = 1 FIGURE 5-3: P13 tinL2ra1l tinL2ra1l tra1V2inL P13 (c) 1996 Microchip Technology Inc. P12 INC PC INC PC DATA_HI OUT DATA_HI IN DATA_HI OUT DATA_HI IN DATA_HI OUT DATA_HI OUT DATA_LO OUT DATA_LO IN DATA_LO OUT DATA_LO IN DATA_LO OUT DATA_LO OUT Program location X Do not increment PC Raise RA1 before RA0 to do this Verify location X Program location X Raise RA1 after RA0 to increment to location X +1 Verify location X +1 Pulse RA1 to increment address to X +2 Verify location X +2 RA1 INC PC RA0 RB<7:0> PROGRAMMING AND VERIFY TIMINGS III RC<7:0> Verify location X Note: Device in PGM mode Test = +5 VPP/MCLR = VPP RA2 = 0 RA3 = 0 RA4 = 1 EPROM Memory Programming Specification DS30139I-page 13 PIC17CXX FIGURE 5-4: POWER-UP/DOWN SEQUENCE FOR PROGRAMMING VDD tvcV2tsH P16 VPP/MCLR tvpL2vcL P19 TEST RA4 RA2 RA3 RA0 P3 tirV2tsH RB<7:0> trbV2mcH E1H P17 P18 tmcH2rbI DS30139I-page 14 (c) 1996 Microchip Technology Inc. EPROM Memory Programming Specification NOTES: (c) 1996 Microchip Technology Inc. DS30139I-page 15 WORLDWIDE SALES & SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com/ Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 214 991-7177 Fax: 214 991-8588 Dayton Microchip Technology Inc. Suite 150 Two Prestige Place Miamisburg, OH 45342 Tel: 513 291-1654 Fax: 513 291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92715 Tel: 714 263-1888 Fax: 714 263-1338 AMERICAS (continued) New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905 405-6279 Fax: 905 405-6253 EUROPE United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1 628 850303 Fax: 44 1 628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041, Agrate Brianza, Milan Italy Tel: 39 39 689 9939 Fax: 39 39 689 9883 ASIA/PACIFIC Hong Kong Microchip Technology Rm 3801B, Tower Two Metroplaza, 223 Hing Fong Road, Kwai Fong, N.T., Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 5/10/96 All rights reserved. (c) 1996, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30139I - page 16 (c) 1996 Microchip Technology Inc. |
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